1. Field of the Invention
The present invention relates to a circuit layout structure. More particularly, the present invention relates to a circuit layout structure with a power circuit and a ground circuit having a sufficient line width to maintain signal integrity during transmission.
2. Description of the Related Art
Due to the rapid development of the electronic industry in recent years, integrated circuit (IC) chips find applications in many areas. To meet the demands of as many customers as possible, semiconductor manufacturers have to increase the level of integration of their IC chips. Hence, the density of input/output terminals in each single chip has to increase correspondingly. In other words, for a conventional wire-bonded chip, either the size of the chip has to be reduced for the same number of signal input/output terminals or the number of signal input/output terminals has to be increased for a chip of a given size. In general, the density of input/output terminals con be increased by dispensing the bonding pads around the active surface of the chip in a multi-tier (three-tier or four-tier) organization.
FIG. 1 is a top view of a section of a conventional circuit layout structure on a chip. FIG. 2 is a cross-sectional view along line I–I′ of FIG. 1. As shown in FIGS. 1 and 2, the chip 50 has a bonding pad area A1 and a nearby device area A2. The chip 50 further comprises a substrate 60 and a circuit layout structure 100. The circuit layout structure 100 essentially comprises a plurality of circuit layers (M1, M2, . . . , M6), a plurality of dielectric layers 110, and a plurality of vias 120. The circuit layers M1, M2, . . . , M6 sequentially stacking over the substrate 60. The dielectric layers 110 sandwiching between adjacent circuit layers M1, M2, . . . , M6. The vias 120 passing through the dielectric layers 110 and electrically connect to various circuit layers (M1, M2, . . . , M6).
The sixth circuit layer M6 (the topmost layer or the layer farthest from the substrate 60) has a plurality of bonding pads 130˜133 within the bonding pad area A1. The bonding pads 130˜133 are organized into a plurality of rows including a first bonding pad row R1, a second bonding pad row R2, a third bonding pad row R3, and a fourth bonding pad row R4. In the conventional circuit layer structure 100, the bonding pads 130 and 131 of the first bonding pad row R1 and the second bonding pad row R2 are signal bonding pads. The bonding pads 132 in the third bonding pad row R3 are power bonding pads and the bonding pads 133 in the fourth bonding pad row R4 are ground bonding pads. Furthermore, the bonding pads 130 and 131 in the first bonding pad row R1 and the second bonding pad row R2 respectively are electrically connected to the second and third circuit layers M2 and M3 through a set of vias 120. Similarly, the bonding pads 132 and 133 in the third bonding pad row R3 and the fourth bonding pad row R4 respectively are electrically connected to the fourth and the fifth circuit layers M4 and M5 through another set of vias 120. Consequently, the power line L1 connecting the boding pads 132 of the third bonding pad row R3 and the ground line L2 connecting the bonding pads 133 of the fourth bonding pad row R4 alternate with the signal line L3 connecting the bonding pads 130 of the first bonding pad row R1 in area S1 and alternate with the signal line L4 connecting the bonding pads 131 of the second bonding pad row R2 in area S2.
FIG. 3 is a cross-sectional view along line II–II′ of FIG. 2. As shown in FIGS. 2 and 3, the power lines L1 and the ground line L2 alternate with the signal line L4 on the left side area S2. Meanwhile, the power line L1 and the ground line L2 alternate with another signal line L3 on the right side area S1. Thus, the line width of the power line L1, the ground line L2, the signal lines L3 and L4 is subjected to some limitations so that the circuit layout of the power line L1 and the ground line L2 is more complicated.
Because the power line and the ground line alternates with the signal line, a portion of the power line and ground line must be narrowed to make way for the passage of the signal line. Yet, the power line and the ground line must have a substantial cross-sectional area for the passage of current. Without increasing the size of a chip, the narrower section in areas where the signal lines alternate with the power line and the ground line in a conventional circuit layout structure is bound to compromise the signal transmission integrity of the chip.